Publications and presentations

This page summarises peer reviewed articles, presentations at conferences and workshops produced by the STEEPER project.
  1. J. Knoch, "Tunnel FETs – Device Principles and Realizations", http://nanohub.org/resources/18723/supportingdocs
  2. J. Knoch, "Gate-Controlled Doping in Carbon-Based FETs",(invited) Joint MRS-JSAP Meeting, Kyoto, 2013
  3. P. Das Kanungo, H. Schmid, M. T. Björk, L. M. Gignac, Ch. Breslin, J. Bruley, C. D. Bessire, H.Riel, "Selective Area Growth of III-V Nanowires and their Heterostructures on Silicon in a Nanotube Template: Towards Monolithic Integration of Nano-Devices". Nanotechnology 24, 225304 2013.
  4. E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani, “Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model”, Solid-State Electronics, Volume 84, June 2013, Pages 96-102.
  5. L. Knoll, Q. T. Zhao, Member, IEEE, A. Nichau, S.Trellenkamp, S. Richter, A. Schäfer, D. Esseni, L. Selmi, K. K. Bourdelle, S. Mantl, Member, IEEE. Inverters with strained Si nanowire complementary tunnel field-effect transistors. EEE Electron Device Letters Volume 34, Issue 6, 2013 doi: 10.1109/LED.2013.2258652
  6. S. Wirths, A. T. Tiedemann, Z. Ikonic, P. Harrison, B. Holländer et al., IBand engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors. Appl. Phys. Lett. 102, 192103 (2013); doi: 10.1063/1.4805034
  7. E. Baravelli, E. Gnani, R. Grassi, A. Gundi and G. Baccarani, “Optimization of Staggered Heterojunction p-TFETs for LSTP and LOP Applications, accepted to Device Research Conference (DRC), 2013.
  8. E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani, “Physics-based analytical model of nanowire tunnel-FETs”, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), p. 1-4.
  9. E. Gnani, S. Reggiani, A. Gnudi, G. Baccarani, “Drain-conductance optimization in nanowire TFETs”, Proceedings of the European Solid-State Device Research Conference (ESSDERC), p. 105-108, 2012.
  10. H. Riel, K.E. Moselund, C. Bessire, M.T. Björk, A. Schenk*, H. Ghonein, H. Schmid, IBM Research, Zurich, *ETH, Zurich, "16.6 InAs-Si Heterojunction Nanowire Tunnel Diodes and Tunnel FETs (Invited)", IEEE International Electron Devices Meeting, San Francisco, 2012.
  11. Eli Yablonovitch, "Density-of-States Switching Mechanism for the Tunnel Field Effect Transistor," UCB, NSF E3S Center Director, "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  12. Cyrille Le Royer; CEA, "Silicon TFET Processing", "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  13. Dr. Heike Riel; IBM Zurich, "Nanoscale IIIV Devices Processing", "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  14. Simon Richter; FZ Juelich, "Strained Si and SiGe nanowire TFETs", "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  15. Thomas Grap; RWTH Aachen, "Electrostatic Doping in Tunnel FETs", "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  16. Prof. G. Baccarani; Uni. Bologna, "Modeling and simulation of SSS Devices", "Steep Slope Switches (SSS) Technologies, Devices, Applications" workshop at the ESSDERC/ESSCIRC Conference in Bordeaux on Sept. 21, 2012.
  17. J. Knoch, "Tunnel FET architectures and device concepts for steep slope switches", SINANO Summer School 2012, Bertinoro
  18. L. Lattanzio, L. De Michielis and A. M. Ionescu, "Electron-Hole Bilayer Tunnel FET for Steep Subthreshold Swing and Improved ON Current", ESSDERC 2011.
  19. L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. M. Ionescu, "Tunnel-FET Architecture with Improved Performance due to Enhanced Gate Modulation of the Tunneling Barrier", DRC 2011 proceedings, pag 111-112;
  20. De Michielis, L., Iellina, M., Palestri, P., Ionescu, A.M., Selmi, L., "Tunneling path impact on semi-classical numerical simulations of TFET devices", 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, art. no. 5758002, pp. 146-149
  21. De Michielis, L., Iellina, M., Palestri, P., Ionescu, A.M., Selmi, L., "Effect of the Choice of the Tunneling Path on Semi-classical Numerical Simulations of TFET devices", S-State Electronics Journal.
  22. M. Schmidt, R. A. Minamisawa, S Richter, J.-M. Hartmann, R. Luptak, A. Tiedemann, D. Buca, Q. T. Zhao, S. Mantl “Impact of strain and Ge concentration on the performance of planar SiGe band- to-band-tunneling transistors” Proc. 2011 12th International Conference on Ultimate Integration on Silicon (ULIS), pp. 202-205, 2011
  23. Q. T. Zhao, C. Sandow, M. Schmidt, S. Richter, S.Mantl “Planar and Nanowire Si-TFETs” Workshop on Simulation and Characterization of Steep-Slope Switches, Bologna, Italy, 09.09.2010
  24. Q. T. Zhao, C. Sandow, M. Schmidt, S. Richter, S.Mantl (invited) “Silicon and Strained Silicon Planar and Nanowire Tunnel FETs” China Semiconductor Technology International Conference, Shanghai, China, March 13-14, 2011
  25. M. Schmidt, R. A. Minamisawa, S Richter, J.-M. Hartmann, R. Luptak, A. Tiedemann, D. Buca, Q. T. Zhao, S. Mantl “Impact of strain and Ge concentration on the performance of planar SiGe Band-to-band-tunneling transistors” 2011 12th International Conference on Ultimate Integration on Silicon (ULIS), Cork, Ireland, March 14-16, 2011
  26. S. Mantl (invited) “Concepts for energy efficient transistors” Workshop on Nanotechnology, Nanomaterials and Nanoreliability, Chemnitz, Germany, May 24, 2011
  27. E. Gnani, S. Reggiani, A. Gnudi and G. Baccarani, "Superlattice-Based Steep-Slope Switch", Proc. of the IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2010.
  28. E. Gnani, S. Reggiani, A. Gnudi and G. Baccarani, "Steep-slope nanowire FET with a superlattice in the source extension", Proc. of the European Solid-State Device Research Conference (ESSDERC), p. 380, 2010.
  29. E. Gnani, S. Reggiani, A. Gnudi and G. Baccarani, "Steep-slope nanowire field-effect transistor (SS-NWFET)", Proc. of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), p.69, 2010.
  30. E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi and G. Baccarani, "Investigation on Superlattice Heterostructures for Steep-Slope Nanowire FETs", Proc. of the Device Research Conference (DRC), 2011.
  31. E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi and G. Baccarani, "An Investigation on Steep-Slope and Low-Power Nanowire FETs", ESSDERC 2011 Conference.
  32. E. Gnani, S. Reggiani, A. Gnudi and G. Baccarani, "Steep-Slope Nanowire FET with a Superlattice in the Source Extension", Solid State Electronics.
  33. M. T. Björk, H. Schmid, C. D. Bessire, K. E. Moselund, H. Ghoneim, E. Lörtscher, S. Karg, H. Riel. Si–InAs heterojunction Esaki tunnel diodes with high current densities. Applied Physics Letters, Vol. 97, 163501, 2010.
  34. C. D. Bessire, M. T. Björk, H. Schmid, A. Schenk, K. B. Reuter, and H. Riel Trap-Assisted Tunneling in Si-InAs Nanowire Heterojunction Tunnel Diodes. submitted.
  35. H. Schmid, K. E. Moselund, M. T. Björk, M. Richter, H. Ghoneim, C. D. Bessire and H. Riel. Fabrication of Vertical InAs-Si Heterojunction Tunnel Field Effect Transistors. 69th Device Research Conference Digest, 2011.
  36. P. Mensch, K. E. Moselund, S. Karg, E. Lörtscher, M. T. Björk, H. Schmid and H. Riel. C-V Measurements of Single Vertical Nanowire Capacitors. 69th Device Research Conference Digest, 2011
  37. K. E. Moselund, M. T. Björk, H. Schmid, C. D. Bessire, H. Ghoneim, P. Mensch and H. Riel Nanowire Tunnel FETs - From All-Silicon Towards Heterostructures. Wilhelm and Else Heraeus Seminar on III-V Nanowires – Growth, Properties and Applications, Bad Honnef, February 2011
  38. H. Riel. Semiconductor Nanowires for Future Electronic Devices. Schottky Seminar, TU Munich, May 2011
  39. H. Riel. Towards Ultimate Scaling and Beyond – The Importance of Research. DPG Industrietag of the German Physical Soceity, Dresden, March 2011.
  40. G. Signorello, S. Karg, E. Lörtscher, M. Björk, H. Schmid, B. Gotsmann, K. Moselund, and H. Riel Uniaxial Strain in Core/Shell III-V Nanowires: Correlation to Electronic Properties. MRS Spring Meeting, San Francisco, 27th April 2011.
  41. K. E. Moselund, M. T. Björk , H. Schmid, C. D. Bessire, H. Ghoneim, S. Karg, E. Lörtscher, P. Mensch and H. Riel Bottom-up Nanowire Tunneling Devices: Towards III-V Tunnel FETs on Silicon MRS Spring Meeting, San Francisco, 27th April 2011.
  42. C. Bessire, M. Björk, H. Schmid, K. Moselund, H. Ghoneim, S. Karg, H. Riel Si-InAs Heterojunction Esaki Tunnel Diodes with High Current Densities. Annual Meeting of the German Physical Society, Dresden, March 2011
  43. H. Riel, “The Future of Nanolectronics” Update Nano 2011, Helsingborg, 22.05.2011.
  44. S. Karg, G. Signorello, E. Lörtscher, M. Björk, H. Schmid, B. Gotsmann, K. Moselund, and H. Riel Uniaxial Strain in Core/Shell III-V Nanowires: Correlation to Electronic Properties. e-MRS Meeting, Nizza, May 2011.
  45. M. T. Björk, H. Schmid, K. E. Moselund, C. Bessire, M. Naterra-Comte, H. Ghoneim, S. Karg, E. Lörtscher, H. Riel Nanowire Tunnel FETs - From All-Silicon towards Heterostructures. MRS Fall Meeting 2010, November, Boston, USA
  46. H. Riel Towards Ultimate Scaling – Semiconducting Nanowires Frontiers of the Nanoelectronics, München, 08.09.2010
  47. H. Riel Nanowire Field Effect Transistors – Where do they belong to? SINANO-NANOSIL Workshop Seville, 17.09.2010
  48. H. Riel, K. Moselund, M. Björk, H. Schmid, H. Ghoneim, C. Bessire, E. Lörtscher, S. Karg, W. Riess Tunnel Field Effect Transistors based on Grown Nanowires. SISPAD Workshop – Simulation and Characterization of Steep-Slope Switches, Bologna, 09.09.2010
  49. Heike Riel, K. Moselund, M. Bjoerk, H. Schmid, H. Ghoneim, E. Loertscher, S. Karg, W. Riess VLS-grown Silicon Nanowires – Growth, Doping, and Tunnel FETs. 2010 IEEE Silicon Nanoelectronics Workshop, Honolulu, 13.06.2010
  50. W. Riess, “The Future of Nanoelectronics”:
  51. W. Riess, “The Future of Nanoelectronics”: Albert-Ludwigs Universität Freiburg, Technische Fakultät, Fakultätskolloquium, July 15, 2010
  52. W. Riess, “The Future of Nanoelectronics”: 457. WE-Heraeus Seminar, Graphene Electronics – Material, Physics and Devices, August 15-18, 2010
  53. W. Riess, “The Future of Nanoelectronics”: Physikalisches Kolloquium, Univeristät Basel, September 24, 2010
  54. W. Riess, “The Future of Nanoelectronics”: EPFL Kolloquium, 8 March 2010
  55. W. Riess, “The Future of Nanoelectronics”: Physikalisches Kolloquium, Universität Regensburg, January 24, 2011
  56. W. Riess, “The Future of Nanoelectronics”: Swedish Foundation for Strategic Research, Lindholmen Science Park, Göteborg, Sweden, May 9‚ 10, 2011
  57. C. Bessire, M. T. Björk, H. Schmid, K. Moselund, H. Ghoneim, P. Mensch, H. Riel, Nanowire Heterostructure Tunnel Devices for Future Transistors, IBM Binnig and Rohrer, Nanotech Center opening, May 2011.
  58. C. Bessire, M. Björk, H. Schmid, K. Moselund, H. Ghoneim, S. Karg, H. Riel, Si-InAs Nanowire Heterojunction Esaki Tunnel Diodes with High Current Densities, Wilhelm and Else Heraeus Seminar on III-V Nanowires – Growth, Properties and Applications, Bad Honnef, February 2011.
  59. Ph. Mensch, K. Moselund, S. Karg, M. Björk, H. Schmid, E. Lörtscher, and H. Riel. Capacitance Measurements of Vertical Wrapped-Gate Nanowire MOS Capacitors. Wilhelm and Else Heraeus Seminar on III-V Nanowires – Growth, Properties and Applications, Bad Honnef, February 2011.
  60. R. Rhyner, C. Bessire, L. De Michielis, A. Biswas, A. Schenk, M. Björk, H. Schmid, H. Riel, A. M. Ionescu, Enabling energy efficient tunnel FET-CMOS co-design by compact modeling and simulation, NanoTera annual meeting, May 2011
  61. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration”, IEEE Electron Device Letters, Vol 33, N° 2, February 2012, pp.179-182
  62. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, “Z2-FET: a steep switching device with gate-controlled hysteresis”, Proc. of the EuroSOI conference, 2012
  63. A. Villalon, C. Le Royer, M. Cassé, D. Cooper, B. Prévitali, C. Tabone, J.-M. Hartmann, P. Perreau, P. Rivallin, J.-F. Damlencourt, F. Allain, F. Andrieu, O. Weber, O. Faynot and T. Poiroux, “Strained Tunnel FETs with record Ion: First demonstration of ETSOI TFETs with SiGe channel and RSD”, 2012 SYMPOSIUM ON VLSI TECHNOLOGY (submitted)
  64. Pino D'Amico, Paolo Marconcini, Gianluca Fiori, Giuseppe Iannaccone "Interband tunneling in nanowires with diamond cubic or zincblende crystalline structure based on atomistic modeling" to submit to Appl. Phys. Lett.
  65. A. Revelant, P. Palestri and L. Selmi "Multi-Subband Semi-classical Simulation of n-type Tunnel-FETs" ULIS 2012
  66. E. Gnani, S. Reggiani, A. Gnudi, G. Baccarani, “Steep-Slope Nanowire FET with a Superlattice in the Source Extension”, Solid-State Electronics, vol. 65-66, pp. 108-113, November-December 2011.
  67. E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani, “Investigation on Superlattice Heterostructures for Steep-Slope Nanowire FETs”, Device Research Conference (DRC 2011), pp. 201-202, Santa Barbara CA, June 20-22, 2011.
  68. E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi and G. Baccarani, "An Investigation on Steep-Slope and Low-Power Nanowire FETs”,Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp. 299-302, Helsinki, 13-15 September 2011.
  69. E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani, “Performance Limits of Superlattice-Based Steep-Slope Nanowire FETs”, Proceedings of the International Electron Device Meeting (IEDM), pp. 5.1.1-5.1.4, Washington DC, 5-7 December, 2011.
  70. Q.T. Zhao, J. M. Hartmann and S. Mantl, “An Improved Si Tunnel Field Effect Transistor with a Buried Strained Si1-xGex Source”, IEEE Electron Device Lett. 32, pp.1480-1482, 2011
  71. Q. T. Zhao, W. J. Yu, B. Zhang, M. Schmidt, S. Richter, D. Buca, J.-M. Hartmann, R. Luptak, A. Fox, K. K. Bourdelle, S. Mantl, “Tunneling Field-Effect Transistor with a Strained Si Channel and a Si0.5Ge0.5 Source”, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp. 251-253, 2011
  72. M. Schmidt, R. A. Minamisawa, S Richter, J.-M. Hartmann, R. Luptak, A. Tiedemann,D. Buca, Q. T. Zhao, S. Mantl “Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors” Proc. 12th International Conference on Ultimate Integration on Silicon (ULIS), pp.202-205, 2011
  73. Q. T. Zhao, C. Sandow, M. Schmidt, S. Richter and S.Mantl (invited talk ) “Planar and Nanowire Si-TFETs” China Semiconductor Technology International Conference (CSTIC), Shanghai, March 13-14, 2011
  74. H. Schmid, K.E. Moselund, M.T. Bjoerk, M. Richter, H. Ghoneim, C.D. Bessire, H. Riel, "Fabrication of Vertical InAs-Si Heterojunction Tunnel Field Effect Transistors", Proc. Device Research Conference "DRC," Santa Barbara, CA (IEEE, June 2011)
  75. K. E. Moselund, M. T. Björk, H. Schmid, H. Ghoneim, S. Karg, E. Lörtscher, W. Riess, H. Riel, “Silicon nanowire tunnel FETs: Low-temperature operation and influence of high-k gate dielectric”, TED 2011
  76. P. Mensch, K.E. Moselund, S. Karg, M.T. Bjoerk, H. Schmid, E. Loertscher, H. Riel, "C-V Measurements of Single Vertical NW Capacitors", Proc. Device Research Conference "DRC," Santa Barbara, CA (IEEE, June 2011)
  77. C. Bessire, M. T. Bjoerk, H. Schmid, A. Schenk, K. B. Reuter, H. Riel, “Trap assisted tunneling inn Si-InAs Nanowire Heterostructure Tunnel Diodes”, Nano Lett. 2011