Device Technology of Si-based tunnel FETs

Partners: CEA, FZJ, IUNET, EPFL

Accomplished Results

  • We have fabricated and characterized SOI Trigate (with Wmin~12nm, H~12nm) planar tunnel FETs (cointegrated with CMOS), showing the interest of i) narrow device width (for electrostatic tunneling enhancement), ii) SiGe:B Raised Source-Drain (for strain-based tunneling increase).
  • SiGe nanowire (NW) homojunction and SiGe/Si NW herterojunction TFETs (with Wmin~30nm) have been obtained and analyzed, highlighting the tunneling efficiency of low band gap material (FZJ).
  • Strained Si NW p- and n-channel TFETs have been realized (by using tilted ion implantation into the silicide and subsequent thermally induced dopant segregation; FZJ). We also demonstrate that the impact of TAT is reduced by improving the electrostatics, for example by using gate-all around (GAA) TFETs with scaled NWs (diameter 10nm). sSi NW TFET inverters have been demonstrated for the first time with functional voltage transfer characteristics (combined by simulation analysis, cf. Modelling & simulation)
  • NW Tunnel FETs cointegrated with CMOS transistors have been successfully fabricated (CEA) on SOI and compressively strained SiGe-On-Insulator 300mm wafers (xGe~20, 25%). Aggressive patterning process have enabled to obtain nanowire TFETs and CMOS with NW size below 5-6nm.
  • Record performance, Ion=488µA/µm, is obtained for p mode TFET at Ioff=0.13nA/µm at Vds=-0.9V with ON & OFF Vg shift equal to 1.5V. Moreover SS as low as 70mV/dec, and even 30mV/dec have been demonstrated.
  • Low temperature measurements (IUNET-Udine, FZJ) performed on different TFETs both suggest that traps could be responsible for unoptimized performance (TAT vs. BTBT processes).
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Fig. 1.a) SEM picture of GAA TFET [1]
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Fig. 1.b) ID-VGS for 20nm and 10nm NW GAA TFETs, indicating smaller SS in narrower NW TFETs due to better electrostatics [1]
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Fig. 1.c) SS-ID for 20nm and 10nm NW GAA TFETs, indicating smaller SS in narrower NW TFETs due to better electrostatics [1]
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Fig. 1.d) Voltage transfer characteristics of a sSi NW TFET inverter [1]
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Fig. 2.a) ID(VG) characteristics of two SiGe based FD TFETs with different body thicknesses. Thinner body leads to increased ION and higher IOFF, with a slight SS slopes improvement (120 vs. 150mV/dec) [2]
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Fig. 2.b) TFET benchmark (p mode) for FD, MuG and NW tunnel FETs structures (including lot 3 NW results: not published)
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Fig. 2.c) SEM picture of a SiGe based NW TFET with 7 size (after NW patterning)

Reference publications

  1. L. Knoll, Q.T. Zhao, A. Nichau, S. Richter, G.V. Luong, S. Trellenkamp, A. Schäfer, L. Selmi, K. K. Bourdelle, S. Mantl, “Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling”, Proc. of IEEE IEDM 2013.

  2. A. Villalon, C. Le Royer, M. Cassé, D. Cooper, J.-M. Hartmann, F. Allain, C. Tabone, F. Andrieu, and S. Cristoloveanu, “Experimental Investigation of the Tunneling Injection Boosters for Enhanced Ion ETSOI Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 60, N° 12, December 2013, pp. 4079-4084.