Modelling and simulation

Partners: EPFL, IUNET, RWTH

Accomplished Results

  • Development of a Multi Sub-band Monte Carlo and a full quantum transport simulator suited to study and optimize the material composition, geometry and doping of homo-junction and hetero-junction TFETs in Si(1-x)Gex and InAs compounds with planar or nanowire geometry (IUNET-UD and IUNET-BO).
  • Calibration of Band-to-band tunneling model parameters for SiGe and InAs, model benchmarking and verification based on experimental results and atomistic simulations (EPFL, IUNET, RWTH).
  • Development and Verilog-A implementation of compact semi-analytical models for Tunnel junctions and TFETs suited for circuit level simulations (EPFL).
  • Understanding the trade-offs among output conductance, on-current and sub-threshold slope of TFETs, and design guidelines for device optimization (IUNET-BO)
  • Simulation of many tunnel-FETs architectures in a variety of material systems and identification of promising and performant options (EPFL, IUNET-UD and IUNET-BO)
  • Mixed device-circuit and look-up table simulation of optimized complementary TFET digital circuits clarified the energy-performance trade off, the minimum energy point and the competitiveness margins for TFETs in an aggressive supply voltage scaling scenario (IUNET-UD and IUNET-BO, EPFL).
Hover over the slide to pause the slideshow
Stacks Image 510
Fig. 1. IV curves of Si TFETs according to calibrated MSMC and quantum codes [1]
Stacks Image 508
Fig.2. Atomistic BTBT transmission and bandgap in Si, Ge and InAs nanowires [2]
Stacks Image 512
Fig. 3. Compact model of Si and Ge Tunnel Junctions [3]
Stacks Image 506
Fig. 4: Full quantum simulation of a new InAs / AlGaSb n- and p-TFET platform providing better performance than multi-gate CMOS at 5sub-0.3V VDD [4]
Stacks Image 504
Fig. 4 continued: Full quantum simulation of a new InAs / AlGaSb n- and p-TFET platform providing better performance than multi-gate CMOS at 5sub-0.3V VDD [4]
Stacks Image 498
Fig. 5: Simulated delay advantage of TFET over SOI and bulk for VDD <350 mV and 450 mV, resp. [7]

References

  1. A.Revelant, P.Palestri, P.Osgnach and L.Selmi, “Calibrated multi-subband Monte Carlo modeling of tunnel-FETs in silicon and III–V channel materials” Solid-State Electronics, Vol.88, Oct. 2013, pp. 54–60
  2. P. D’Amico, P.Marconcini, G.Fiori, G. Iannaccone, “Engineering Interband Tunneling in Nanowires With Diamond Cubic or Zincblende Crystalline Structure Based on Atomistic Modeling”, IEEE Trans. Nanotechnology. Vol. 12, n. 5, pp. 839-842, 2013.
  3. L. De Michielis, N. Dagtekin, A. Biswas, L. Lattanzio, L. Selmi, M. Luisier, H. Riel, and A. M. Ionescu, “An innovative band-to-band tunneling analytical model and implications in compact modeling of tunneling-based devices “ Appl. Phys. Lett. 103, 123509 (2013)
  4. E.Baravelli, E.Gnani, A.Gnudi, G.Baccarani, IEEE TED, DOI: 10.1109/TED.2013.2294792
  5. A.Biswas, N.Dagteki, W.Grabinski, A.Bazigos, C.Le Royer, O.Faynot, A.M.Ionescu “A study on 1T Capacitor-less Tunnel FET DRAM Exploiting Ungated Body” Proc, ISDRS Conf., pp.11-13, 2013
  6. S.S.Dan, A. Biswas, C. L. Royer, W. Grabinski and A. M. Ionescu. A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction, in IEEE Electron Device Letters, vol. 33, num. 2, p. 140-142, 2012.
  7. D.Esseni, M.Guglielmini, B.Kapidani, T.Rollo, and A.Alioto, “Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits, submitted to IEEE Trans. VLSI.