Benchmarking and Integration of Tunnel FETs into nano-CMOS

Partners: CEA LETI, EPFL, FZJ, GF, IBM, IMC, IUNET

Accomplished Results

  • Device Requirements specified

    TFET transistors were assessed for high performance logic (HP), low operational power (LOP) and low standby power (LSP) applications. It turned out that the most promising field of application is the area of low operational power. Here low supply voltages are required. A full replacement in HP platform was ruled out.

    Furthermore, a full set of device requirements for full replacement, add on and niche applications was defined.

  • Potential CMOS process compatibility of TFET flows assessed

    Since the projected TFET performance appears to be well below traditional CMOS technology process options for co-integration into CMOS process flows have been investigated. The following numbers reflecting costs have been obtained:

    Bulk Si CMOS reference: 100%
    FD SOI CMOS: 109%
    FD SOI CMOS + Si TFET: 115%
    Bulk Si CMOS + III-V TFET: 128%
    Net outcome is that the co-integraton is feasible but would add significant complexity on today´s platforms

  • Bench mark for DC, AC and analog properties carried out

    DC-Performance: III-V based TFET´s achieve the highest drive currents whereas Si-based TFET´s provide lowest Ioff; however, no experimental data demonstrated in target region of low Ioff and high drive currents.

    In order to achieve high drive currents extremely high source doping levels are required. Due to process variations a potential risk on overall device variation is expected.

    It is noteworthy though that excellent sub threshold swings with values well below 60mV/dec have been demonstrated for TFET´s.

    Due to its nature of operation TFET´s show little to no temperature dependency. This would hinder the realization of voltage reference / band gap circuits based on TFET devices only.

    Overall, due to the shortfall compared to state-of-the-art CMOS technology a full replacement of the latter one is ruled out.

  • Suitability study for low power components

    AC-Performance & power consumptions: As far as RO performance is concerned there is a benefit expected for TFET´s operating at supply voltages of 300mV and below. In addition, the simulated power consumption as well as the energy delay product are in favor for low supply voltages. However, the absolute performance achieved in that voltage ranges is by far not compatible to today´s technologies at their elevated supply voltages.

    Given this fact, applications can be thought of where extremely long battery lifetimes are much more important than performance requirements (e.g. in health care).

Hover over the slide to pause the slideshow
Stacks Image 548
Fig. 1: Ion vs Ioff for published experimental TFETs in recent years; contributions by STEEPER project partners in red.
Stacks Image 546
Fig. 2: Inverter small-signal voltage gain around logic threshold vs. VDD.

References

  1. T. Schulz, et al.: “Tunnel Field Effect Transistors (TFETs) – Technology, Devices, Applications”, MOS-AK/GSA-Workshop, 12.04.2013, Munich